Vasantha Kumar Yernagula vyernagula@broadcom.com & | Currently working as PD Lead handling Netlist2gds at block/subsystem level. Experience: ASIC Physical Design (netlist to GDS activities). Block/FullChip level Physical Design. PD Flow set up, Perl/Tcl scripting.

Vasantha Kumar Yernagula

Currently working as PD Lead handling Netlist2gds at block/subsystem level. Experience: ASIC Physical Design (netlist to GDS activities). Block/FullChip...

Broadcom, 4th Floor, India

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Vasantha Kumar Yernagula’s Emails [email protected]

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Vasantha Kumar Yernagula’s Location Broadcom, 4th Floor, India

Vasantha Kumar Yernagula’s Expertise Currently working as PD Lead handling Netlist2gds at block/subsystem level. Experience: ASIC Physical Design (netlist to GDS activities). Block/FullChip level Physical Design. PD Flow set up, Perl/Tcl scripting.

Vasantha Kumar Yernagula’s Current Industry Intel

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Work Experience

Intel

Soc Design Engineer

Sat Jan 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Samsung Semiconductor

Physical Design Engineer

Thu Jul 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Dec 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)

Broadcom

Ic Design Engineer

Mon Sep 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jun 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)

Achronix Semiconductor

Senior Design Engineer

Fri Mar 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Aug 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)

Sankalp Semiconductor

Design Engineer

Sat Jan 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jul 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)

Tsmc

Engineer

Wed Aug 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat May 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)

Broadcom

Ic Design Engineer

— Present

Skills

Languages

FAQ About Vasantha Kumar Yernagula

Vasantha Kumar Yernagula is located at
Broadcom, 4th Floor, India

Vasantha Kumar Yernagula is a
Currently working as PD Lead handling Netlist2gds at block/subsystem level. Experience: ASIC Physical Design (netlist to GDS activities). Block/FullChip level Physical Design. PD Flow set up, Perl/Tcl scripting. Intel

Vasantha Kumar Yernagula currently works in the
Intel

Vasantha Kumar Yernagula specializes in
Currently working as PD Lead handling Netlist2gds at block/subsystem level. Experience: ASIC Physical Design (netlist to GDS activities). Block/FullChip level Physical Design. PD Flow set up, Perl/Tcl scripting.

Vasantha Kumar Yernagula speaks the following languages:
No languages available.

Vasantha Kumar Yernagula has prior experience in the following industries:
Samsung Semiconductor , Broadcom , Achronix Semiconductor , Sankalp Semiconductor , Tsmc

Vasantha Kumar Yernagula has the following professional experience:
Intel , Samsung Semiconductor , Broadcom , Achronix Semiconductor , Sankalp Semiconductor , Tsmc , Broadcom .